1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device having a plurality of elements provided in one well region and a method of manufacturing this semiconductor device.
2. Description of the Related Art
Well known as a semiconductor device having a well region is a CMOS device in which N-channel MOSFETs and P-channel MOSFETs (hereinafter referred to as "NMOSs" and "PMOSs") constitute a desired circuit. CMOS devices are now widely used in almost all types of semiconductor ICs including logic ICs, semiconductor memories, 1-chip micro-computers and the like.
The elements of CMOS integrated circuits are being made smaller and smaller, and the integration density of CMOS integrated circuits is increasing. As the integration density increases, the impurity concentration of the substrate or well region of each CMOS integrated circuit is generally increased in order to electrically isolate the elements more reliably or to improve the short-channel effect of transistors.
However, the higher the impurity concentration of the well region, the more prominent the influence of the back-gate bias effect, which effect has hitherto been neglected. Inevitably, the NMOSs and PMOSs provided in the well region have threshold voltages much higher than design values. In particular, a MOSFET having a small channel width has its threshold voltage markedly increased due to the back-gate bias effect. The more its threshold voltage is raised, the more the MOSFET will be deteriorated in terms of current-driving ability.
The trend has been that the number of functions performed by CMOS integrated circuits has increased. In other words, more and more circuits of various functions are incorporated in one chip. A single chip contains blocks having high integration density (e.g., the core of a semiconductor memory) and blocks having low integration density (e.g., a voltage booster and an input/output circuit). The MOSFETs incorporated in any high-density block differ in size from those provided in any low-density block. The difference in MOSFET size increases in proportion to the integration density of the high-density block, as is observed at present in the CMOS integrated circuits.
The greater the difference in MOSFET size between a high-density block and a low-density block becomes, the more difficult it is for the MOSFETs to have respective threshold voltages at the design values. This is because channel ions need to be implanted to form MOSFETs in many separate steps under different conditions selected in accordance with the sizes of the MOSFETs. As many masks as the steps of implanting channel ions are required. The many steps performed and the many masks increase the manufacturing cost of, and decreases the yield of, the CMOS integrated circuit.
There is known a CMOS device which has a plurality of well regions having different impurity concentrations so that MOSFETs provided in them may have respective threshold voltages of design values. Such a CMOS device is disclosed in Jpn. Pat. Appln. KOKAI Publication No. 4-3468. Having different impurity concentrations and formed in a substrate, the well regions must be spaced apart from one another by some distance. Furthermore, each well region needs to have a contact hole for applying bias potentials. As a consequence, the CMOS device cannot be made small.